Devices for delaying digital data are commonly referred to as digital delay lines. In general, a digital delay line receives a series of digital data elements S(n), as shown in FIG. 1A, where n is an integer, for all n from 1 to MAX, where MAX is an integer designating the end of the digital data series. Each digital data element can be a single bit or a multiple bit packet. The series of digital data elements can equivalently be expressed as a continuous function of time SC(t), as shown in FIG. 1B. The value of SC(t) changes abruptly at t==nT and maintains a constant value of S(nT) from nT&lt;t&lt;(n+1)T, for all n from 1 to MAX, where T is the time between consecutive digital data elements. The digital delay line produces SC(t-.tau.), which is a delayed version of SC(t), where .tau. is the amount of delay through the digital delay line. In general, .tau. can be any non-zero value, but prior art embodiments of digital delay lines often limit .tau. to an even multiple of T.
Digital delay lines have many applications in electronic systems. For example, digital filters use digital delay lines to generate a set of delayed versions of a common series of digital data elements. Each version is scaled, and the set of scaled, delayed digital data elements are summed to accomplish the filtering. Such filters typically use digital delay lines with .tau.'s less than 10T, which can be implemented with edge-triggered D-type or J-K flip-flops.
Some applications require a delay having a .tau. of 1000T or more. In such cases, the use of flip-flops is inefficient, due to the length of the delay and/or the number of data bits in each data element. As an example, consider an application which requires a running average of 512 data elements of a series of digital data elements. An implementation of such an averaging function is to duplicate the series of digital data elements, send the original series into an accumulator, and send the duplicate into a delay line with a .tau. of 512T. The output of the delay line is subtracted from the accumulator so that the accumulator's output is always the sum of the 512 data elements in the delay line. If each data element of the series of digital data elements is 8 bits wide, implementing the delay line with flip-flops would require 512 times eight, or 4096 flip-flops, each clocked with a clocking signal having a frequency of 1/T.
A prior-art alternative to using flip-flops to implement the 512 data element digital delay line is to enter each data element of the series in a digital data storage device such as a RAM, then extract each data element at a later time, so that the amount of time the data element remains in the RAM is equal to the desired delay. Such a function can be implemented using a 512 by eight bit RAM and a nine bit, modulo 512 address counter. A clocking signal increments the counter at a frequency of 1/T, so that the address to the RAM changes for each new data element available. For each address, the old value entered into the addressed location is extracted before the new data element is entered. Since the counter is modulo 512, a first data element entered into the RAM won't be extracted from the RAM until 511 subsequent data elements are entered into all of the subsequent RAM locations. When the 512.sup.th data element is available, the first data element is extracted from RAM, subjecting the first data element to an effective delay of 512T.
The RAM and counter architecture is efficient in terms of hardware requirements, but it lacks versatility. If the entry and extraction addresses are fixed relative to each other as described in the previous paragraph, the resolution of the delay is limited to T. The maximum delay is bounded by the size of the RAM. The length of the delay can be shortened if the modulo of the counter is changed to a value smaller than the total number of address locations in the RAM. However, if the counter's modulo is changed to a smaller value while a series of digital data elements is being delayed, a set of consecutive data elements from the series of digital data elements will be excised from the output series of delayed digital data elements. When the counter modulo changes, a portion of the RAM is no longer used, and the data elements stored in those locations when the modulo is changed will no longer be accessed, and will be missing from the delayed series of digital data elements.
Similarly, when the length of the delay line is increased, the portion of RAM which was not being used prior to the increase is accessible. The data elements extracted for the first time after increasing the counter modulo are undefined with respect to the delayed series of digital data elements. The undefined data effectively creates a gap of undefined data elements in the delayed series of digital data elements.
Many applications cannot tolerate such a corruption of a series of digital data elements. An example of such an application is a transmitter distribution network for a mobile radio system, in which a single source distributes information to several transmitter stations. For optimum performance of the system, the phase of the distributed data should be the same at each transmitter station, which can only be accomplished if the delay path lengths of the data links from the central source to each of the transmitter stations are the same. When a commercial network is used to distribute the data, the longest delay path is determined using methods known to those skilled in the art, and delay lines such as the invention are inserted in the shorter delay paths to equalize the delays. Due to equipment malfunction or natural disaster, the data link with the longest delay path can be disrupted. To remedy such a situation, the commercial network will re-route the failed data link. The new, re-routed data path is unlikely to have the same delay as the path used prior to the disruption, so the longest path must again be determined and the shorter paths must again be equalized. Use of prior art delay lines in such an application will either create a gap in the series of digital data elements or excise data from the series of digital data elements, depending upon whether the delay is lengthened or shortened. Either result will degrade the communications link.
There is a need for a digital delay line whose delay length can be changed while processing a series of digital data elements without disrupting the series of digital data elements by either losing data or creating a gap of undefined data elements in the series.
It is therefore an object of the invention to provide an improved digital delay line whose delay length can be changed while processing a series of digital data elements without disrupting the series of digital data elements by either excising data or creating a gap.
Other objects and advantages of the present invention will become apparent upon consideration of the appended drawings and description thereof.